Publication:
Exploring Instruction Fusion Opportunities in General Purpose Processors

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dc.contributor.authorSingh, Sawan
dc.contributor.authorPerais, Arthur
dc.contributor.authorJimborean, Alexandra
dc.contributor.authorRos, Alberto
dc.contributor.departmentIngeniería y Tecnología de Computadores
dc.date.accessioned2022-10-21T10:32:11Z
dc.date.available2022-10-21T10:32:11Z
dc.date.issued2023-12-18
dc.description© 2023. IEEE. This document is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0 This document is the accepted version of a published work that appeared in final form in MICRO '22: Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture To access the final work, see DOI: https://doi.org/10.1109/MICRO56248.2022.00026
dc.description.abstractThe Complex Instruction Set Computer (CISC) paradigm has led to the introduction of instruction cracking in which an architectural instruction is divided into multiple microarchitectural instructions (μ-ops). However, the dual concept, instruction fusion is also prevalent in modern microarchitectures to maximize resource utilization. In essence, some architectural instructions are too complex to be executed as a unit, so they should be cracked, while others are too simple to waste resources on executing them as a unit, so they should be fused with others. In this paper, we focus on instruction fusion and explore opportunities for fusing additional instructions in a high- performance general purpose pipeline. We show that enabling fusion for common RISC-V idioms improves performance by 7%. Then, we determine experimentally that enabling fusion only for memory instructions achieves 86% of the potential of fusion in this particular case. Finally, we propose the Helios microarchitecture, able to fuse non-consecutive and non-contiguous memory instructions, and discuss microarchitectural changes required to do so efficiently while preserving correctness. Helios allows to fuse an additional 5.5% of dynamic instructions, yielding a 14.2% performance uplift over no fusion (8.2% over baseline fusion).es
dc.formatapplication/pdfes
dc.format.extent14es
dc.identifier.citationMICRO '22: Proceedings of the 55th Annual IEEE/ACM International Symposium on MicroarchitectureOctober 2022 Pages 199–212
dc.identifier.doihttps://doi.org/10.1109/MICRO56248.2022.00026
dc.identifier.eissn978-1-6654-6272-3
dc.identifier.urihttp://hdl.handle.net/10201/124785
dc.languageenges
dc.publisherIEEE Press
dc.relationEuropean Research Council (ERC) under the European Union s Horizon 2020 research and innovation programme (ECHO: Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures, grant agreement No 819134, Consolidator Grant, 2018).es
dc.relation.ispartof55th International Symposium on Microarchitecture (MICRO)es
dc.rightsinfo:eu-repo/semantics/openAccesses
dc.rightsAtribución 4.0 Internacional*
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectGeneral purpose processorses
dc.subjectMicroarchitecturees
dc.subjectInstruction fusiones
dc.titleExploring Instruction Fusion Opportunities in General Purpose Processorses
dc.typeinfo:eu-repo/semantics/articlees
dspace.entity.typePublicationes
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