Publication:
Composite Instruction Prefetching

Simple item page
dc.contributor.authorChacon, Gino
dc.contributor.authorGarza, Elba
dc.contributor.authorJimborean, Alexandra
dc.contributor.authorRos, Alberto
dc.contributor.authorGratz, Paul
dc.contributor.authorJimenez, Daniel A.
dc.contributor.authorMirbagher-Ajorpaz, Samira
dc.contributor.departmentIngeniería y Tecnología de Computadores
dc.date.accessioned2023-06-28T11:00:34Z
dc.date.available2023-06-28T11:00:34Z
dc.date.created2022-10
dc.date.issued2022-10
dc.description© 2022. The authors. This document is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0 This document is the accepted version of a published work that appeared in final form in 40th IEEE International Conference on Computer Design (ICCD). To access the final work, see DOI: https://doi.org/10.1109/ICCD56317.2022.00076
dc.description.abstractPrefetching is a pivotal mechanism for effectively masking latencies due to the processor/memory performance gap. Instruction prefetchers prevent costly instruction fetch stalls by requesting blocks of instruction memory in advance of their use to keep the pipeline front-end busy. the rapidly increasing instruction footprints of modern workloads have amplified the importance of such research. We propose a framework to leverage the complementary prefetching behaviors of existing prefetching techniques to create composite prefetchers. We show that recently proposed instruction prefetching techniques leverage different mechanisms from one another and find that in many cases, different prefetchers are complementary to each other. Composite prefetching allows for higher performance at lower storage overheads by combining the coverage of different complex prefetchers. We demonstrate a framework for selecting and combining state-of-the-art complex prefetchers, in a ”plug-and-play” fashion, to identify the best performing combinations at various hardware overheads. We show that for every storage capacity constraint analyzed, composite prefetching outperforms prior prefetching schemes with greater improvements shown at smaller capacity constraints.es
dc.formatapplication/pdfes
dc.format.extent8es
dc.identifier.citation40th IEEE International Conference on Computer Design (ICCD)
dc.identifier.doihttps://doi.org/10.1109/ICCD56317.2022.00076
dc.identifier.eissn978-1-6654-6187-0
dc.identifier.issn1063-6404
dc.identifier.urihttp://hdl.handle.net/10201/132445
dc.languageenges
dc.publisherIEEE Computer Societyes
dc.relationEuropean Research Council (ERC) under the European Union\u2019s Horizon 2020 research and innovation programme (ECHO: Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures, grant agreement No 819134, Consolidator Grant, 2018).es
dc.relation.ispartofInternational Conference on Computer Design (ICCD)es
dc.rightsinfo:eu-repo/semantics/openAccesses
dc.rightsAtribución 4.0 Internacional*
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectInstruction prefetchinges
dc.subjectFirst-level cacheses
dc.subjectDatacenter applicationses
dc.subjectHardware prefetchinges
dc.subjectHnstruction cacheses
dc.titleComposite Instruction Prefetchinges
dc.typeinfo:eu-repo/semantics/articlees
dspace.entity.typePublicationes
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
gchacon-iccd22.pdf
Size:
497.14 KB
Format:
Adobe Portable Document Format
Description:
Download
License bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
license.txt
Size:
2.26 KB
Format:
Item-specific license agreed upon to submission
Description:
Download
Collections
Artículos