Publication: Composite Instruction Prefetching
Authors
Chacon, Gino ; Garza, Elba ; Jimborean, Alexandra ; Ros, Alberto ; Gratz, Paul ; Jimenez, Daniel A. ; Mirbagher-Ajorpaz, Samira
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Publisher
IEEE Computer Society
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DOI
https://doi.org/10.1109/ICCD56317.2022.00076
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info:eu-repo/semantics/article
Description
© 2022. The authors. This document is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0
This document is the accepted version of a published work that appeared in final form in 40th IEEE International Conference on Computer Design (ICCD).
To access the final work, see DOI: https://doi.org/10.1109/ICCD56317.2022.00076
Abstract
Prefetching is a pivotal mechanism for effectively masking latencies due to the processor/memory performance gap. Instruction prefetchers prevent costly instruction fetch stalls by requesting blocks of instruction memory in advance of their use to keep the pipeline front-end busy. the rapidly increasing instruction footprints of modern workloads have amplified the importance of such research.
We propose a framework to leverage the complementary prefetching behaviors of existing prefetching techniques to create composite prefetchers. We show that recently proposed instruction prefetching techniques leverage different mechanisms from one another and find that in many cases, different prefetchers are complementary to each other. Composite prefetching allows for higher performance at lower storage overheads by combining the coverage of different complex prefetchers. We demonstrate a framework for selecting and combining state-of-the-art complex prefetchers, in a ”plug-and-play” fashion, to identify the best performing combinations at various hardware overheads. We show that for every storage capacity constraint analyzed, composite prefetching outperforms prior prefetching schemes with greater improvements shown at smaller capacity constraints.
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Citation
40th IEEE International Conference on Computer Design (ICCD)
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