A Dual-Consistency Cache Coherence Protocol

Jimborean, Alexandra; Ros Bardisa, Alberto

Publication:
A Dual-Consistency Cache Coherence Protocol

dc.contributor.author	Jimborean, Alexandra
dc.contributor.author	Ros Bardisa, Alberto
dc.contributor.department	Ingeniería y Tecnología de Computadores
dc.date.accessioned	2024-02-08T11:52:38Z
dc.date.available	2024-02-08T11:52:38Z
dc.date.issued	2015-05-25
dc.description	© 2015. The authors. This document is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0 This document is the accepted version of a published work that appeared in final form in 2015 IEEE International Parallel and Distributed Processing Symposium. To access the final work, see DOI: https://doi.org/10.1109/IPDPS.2015.43
dc.description.abstract	Weak memory consistency models can maximize system performance by enabling hardware and compiler optimizations, but increase programming complexity since they do not match programmers’ intuition. The design of an efficient system with an intuitive memory model is an open challenge. This paper proposes SPEL, a dual-consistency cache coherence protocol which simultaneously guarantees the strongest memory consistency model provided by the hardware and yields improvements in both performance and energy consumption. The design of the protocol exploits a compile-time identification of code regions which can be executed under a less restrictive, thus optimized protocol, without harming correctness. Outside these regions, code is executed under a more restrictive protocol which enforces sequential consistency. Compared to a standard directory protocol, we show improvements in performance of 24% and reductions in energy consumption of 32%, on average, for a 64-core chip multiprocessor.	es
dc.format	application/pdf	es
dc.format.extent	10	es
dc.identifier.doi	https://doi.org/10.1109/IPDPS.2015.43
dc.identifier.eissn	978-1-4799-8648-4
dc.identifier.issn	Print: 1530-2075
dc.identifier.uri	http://hdl.handle.net/10201/138988
dc.language	eng	es
dc.publisher	IEEE	es
dc.relation	This work was supported in part by the”Fundacion Seneca Agencia de Ciencia yTecnologıa de la Region de Murcia” undergrant ”Jovenes Lıderes en Investigacion” 18956/JLI/13, by the Spanish MINECO ,by European Commission FEDER funds,undergrant TIN2012-38341-C04-03,as well as by the Swedish Research Council UPMARC Linnaeus Centre and by the VR frame project ”Efficient Modeling of Heterogeneity in the Era of Dark Silicon”:106201305/C0533201.	es
dc.relation.ispartof	29th International Parallel & Distributed Processing Symposium (IPDPS) pp. 1119-1128	es
dc.relation.publisherversion	http://webs.um.es/aros/papers/pdfs/aros-ipdps15.pdf	es
dc.rights	info:eu-repo/semantics/openAccess	es
dc.rights	Attribution-NonCommercial-NoDerivatives 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/4.0/	*
dc.subject	Protocol	es
dc.subject	SPEL	es
dc.title	A Dual-Consistency Cache Coherence Protocol	es
dc.type	info:eu-repo/semantics/article	es
dspace.entity.type	Publication	es