Publication: A Dual-Consistency Cache Coherence Protocol
Authors
Jimborean, Alexandra ; Ros Bardisa, Alberto
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Publisher
IEEE
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DOI
https://doi.org/10.1109/IPDPS.2015.43
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info:eu-repo/semantics/article
Description
© 2015. The authors.
This document is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0
This document is the accepted version of a published work that appeared in final form in 2015 IEEE International Parallel and Distributed Processing Symposium.
To access the final work, see DOI: https://doi.org/10.1109/IPDPS.2015.43
Abstract
Weak memory consistency models can maximize
system performance by enabling hardware and compiler optimizations,
but increase programming complexity since they do
not match programmers’ intuition. The design of an efficient
system with an intuitive memory model is an open challenge.
This paper proposes SPEL, a dual-consistency cache coherence
protocol which simultaneously guarantees the strongest memory
consistency model provided by the hardware and yields improvements
in both performance and energy consumption. The
design of the protocol exploits a compile-time identification of
code regions which can be executed under a less restrictive,
thus optimized protocol, without harming correctness. Outside
these regions, code is executed under a more restrictive protocol
which enforces sequential consistency. Compared to a standard
directory protocol, we show improvements in performance of
24% and reductions in energy consumption of 32%, on average,
for a 64-core chip multiprocessor.
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