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Muñoz Martínez, Francisco

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Muñoz Martínez, Francisco
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Universidad de Murcia. Departamento de Ingeniería y Tecnología de Computadores

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    STONNE: enabling cycle-level microarchitectural simulation for DNN Inference accelerators
    (IEEE, 2022-01-13) Muñoz Martínez, Francisco; Abellán Miguel, José Luis; Acacio Sánchez, Manuel Eugenio; Krishna, Tushar; Ingeniería y Tecnología de Computadores; Facultad de Informática
    The design of specialized architectures for accelerating the inference procedure of Deep Neural Networks (DNNs) is a booming area of research nowadays. While first-generation rigid accelerator proposals used simple fixed dataflows tailored for dense DNNs, more recent architectures have argued for flexibility to efficiently support a wide variety of layer types, dimensions, and sparsity. As the complexity of these accelerators grows, the analytical models currently being used for design-space exploration are unable to capture execution-time subtleties, leading to inexact results in many cases as we demonstrate. This opens up a need for cycle-level simulation tools to allow for fast and accurate design-space exploration of DNN accelerators, and rapid quantification of the efficacy of architectural enhancements during the early stages of a design. To this end, we present STONNE (Simulation TOol of Neural Network/Engines), a cycle-level microarchitectural simulation framework that can plug into any high-level DNN framework as an accelerator device and perform full-model evaluation (i.e. we are able to simulate real, complete, unmodified DNN models) of state-of-the-art rigid and flexible DNN accelerators, both with and without sparsity support. As a proof of concept, we use STONNE in three use cases: i) a direct comparison of three dominant inference accelerators using real DNN models; ii) back-end extensions and iii) front-end extensions of the simulator to showcase the capability of STONNE to rapidly and precisely evaluate data-dependent optimizations.
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    Flexagon: a multi-dataflow sparse-sparse matrix multiplication accelerator for efficient DNN processing
    (Association for Computing Machinery, 2023-03-25) Garg, Raveesh; Pellauer, Michael; Krishna, Tushar; Muñoz Martínez, Francisco; Abellán Miguel, José Luis; Acacio Sánchez, Manuel Eugenio; Ingeniería y Tecnología de Computadores; Facultad de Informática
    Sparsity is a growing trend in modern DNN models.Existing Sparse-Sparse Matrix Multiplication (SpMSpM) accel-erators are tailored to a particular SpMSpM dataflow (i.e., InnerProduct, Outer Product or Gustavson’s), which determines theiroverall efficiency. We demonstrate that this static decision inher-ently results in a suboptimal dynamic solution. This is becausedifferent SpMSpM kernels show varying features (i.e., dimensions,sparsity pattern, sparsity degree), which makes each dataflow bettersuited to different data sets.In this work we present Flexagon, the first SpMSpM reconfig-urable accelerator that is capable of performing SpMSpM computa-tion by using the particular dataflow that best matches each case.Flexagon accelerator is based on a novel Merger-Reduction Net-work (MRN) that unifies the concept of reducing and merging inthe same substrate, increasing efficiency. Additionally, Flexagonalso includes a new L1 on-chip memory organization, specificallytailored to the different access characteristics of the input and out-put compressed matrices. Using detailed cycle-level simulation ofcontemporary DNN models from a variety of application domains,we show that Flexagon achieves average performance benefits of4.59×, 1.71×, and 1.35×with respect to the state-of-the-art SIGMA-like, SpArch-like and GAMMA-like accelerators (265%, 67%, and18%, respectively, in terms of average performance/area efficiency).
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