Abellán Miguel, José Luis

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Abellán Miguel, José Luis

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Abellán Miguel, José Luis

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Universidad de Murcia. Departamento de Ingeniería y Tecnología de Computadores

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QuCo: efficient and flexible hardware-driven automatic configuration of tile transfers in GPUs
(IEEE Computer Society Press, 2025-12-16) Meseguer, Nicolás; Xu, Daoxuan; Sun, Yifan; Pellauer, Michael; Abellán Miguel, José Luis; Acacio Sánchez, Manuel Eugenio; Ingeniería y Tecnología de Computadores; Facultades de la UMU::Facultad de Informática
The growing complexity and parallelism demands of modern GPU workloads have driven architectural innovations toward \emph{asynchronous tile transfers} (ATTs) to overlap computation and data movement. While ATT units such as the NVIDIA’s Tensor Memory Accelerator (TMA) introduce high-throughput memory transfers, programmers must deal with wavefront specialization, select tile sizes, queue slots, and synchronization primitives, all of which are hardware-specific and workload-dependent. Existing GPU libraries fall short—offering limited ATT support and configurability—so developers still resort to manual exploration of this vast parameter space, which is laborious, error-prone, and fundamentally limits performance portability across GPUs. In this work, we present QuCo (Queue Configurator), a single lightweight hardware unit embedded in the GPU that fully automates the ATT configuration process. Inspired by Blackwell GPU design, QuCo includes a compact \mbox{RISC-V} processor, small memory structures for instructions and data, and a GPU Specification Table (GST) storing key architectural parameters. Using the GST and workload characteristics, along with built-in heuristics, QuCo computes optimal queue configurations at kernel launch. This relieves the programmer of the tedious, time-consuming task of tuning and offline profiling, while simultaneously increasing post-compilation performance portability.
Open Access
STONNE: enabling cycle-level microarchitectural simulation for DNN Inference accelerators
(IEEE, 2022-01-13) Muñoz Martínez, Francisco; Abellán Miguel, José Luis; Acacio Sánchez, Manuel Eugenio; Krishna, Tushar; Ingeniería y Tecnología de Computadores; Facultad de Informática
The design of specialized architectures for accelerating the inference procedure of Deep Neural Networks (DNNs) is a booming area of research nowadays. While first-generation rigid accelerator proposals used simple fixed dataflows tailored for dense DNNs, more recent architectures have argued for flexibility to efficiently support a wide variety of layer types, dimensions, and sparsity. As the complexity of these accelerators grows, the analytical models currently being used for design-space exploration are unable to capture execution-time subtleties, leading to inexact results in many cases as we demonstrate. This opens up a need for cycle-level simulation tools to allow for fast and accurate design-space exploration of DNN accelerators, and rapid quantification of the efficacy of architectural enhancements during the early stages of a design. To this end, we present STONNE (Simulation TOol of Neural Network/Engines), a cycle-level microarchitectural simulation framework that can plug into any high-level DNN framework as an accelerator device and perform full-model evaluation (i.e. we are able to simulate real, complete, unmodified DNN models) of state-of-the-art rigid and flexible DNN accelerators, both with and without sparsity support. As a proof of concept, we use STONNE in three use cases: i) a direct comparison of three dominant inference accelerators using real DNN models; ii) back-end extensions and iii) front-end extensions of the simulator to showcase the capability of STONNE to rapidly and precisely evaluate data-dependent optimizations.
Open Access
Accelerating finite field arithmetic for homomorphic encryption on GPUs
(IEEE Computer Society, 2023-03-14) Livesay, Neal; Jonatan, Gilbert; Mora, Evelio; Shivdikar, Kaustubh; Agrawal, Rashmi; Joshi, Ajay; Kim, John; Kaeli, David; Abellán Miguel, José Luis; Ingeniería y Tecnología de Computadores; Facultad de Informática
Fully homomorphic encryption (FHE) is a rapidly developing technology that enables computation directly on encrypted data, making it a compelling solution for security in cloud-based systems. In addition, modern FHE schemes are believed to be resistant to quantum attacks. Although FHE offers unprecedented potential for security, current implementations suffer from prohibitively high latency. Finite field arithmetic operations, particularly the multiplication of high-degree polynomials, are key computational bottlenecks. The parallel processing capabilities provided by modern GPUs make them compelling candidates to target these highly parallelizable workloads. In this article, we discuss methods to accelerate polynomial multiplication with GPUs, with the goal of making FHE practical.
Open Access
GPU Acceleration of Sparse Fully Homomorphic Encrypted DNNs
(2026-04-13) D'Agata, Lara; Agulló-Domingo, Carlos; Vera-López, Óscar; Shivdikar, Kaustubh; Yudha, Ardhi W. B.; Yaman, Ferhat; Kaeli, David; Abellán Miguel, José Luis; Colbert, Ian; Cano, José; Ingeniería y Tecnología de Computadores; Facultades de la UMU::Facultad de Informática
Fully homomorphic encryption (FHE) has recently attracted significant attention as both a cryptographic primitive and a systems challenge. Given the latest advances in accelerated computing, FHE presents a promising opportunity for progress, with applications ranging from machine learning to information security. We target the most computationally intensive operation in deep neural networks from a hardware perspective, matrix multiplication (matmul), and adapt it for execution on AMD GPUs. We propose a new optimized method that improves the runtime and complexity of ciphertext matmul by using FIDESlib, a recent open-source FHE library designed specifically for GPUs. By exploiting sparsity in both operands, our sparse matmul implementation outperforms its CPU counterpart by up to 3.0\times and reduces the time complexity from cubic to semi-linear, demonstrating an improvement over existing FHE matmul implementations.
Open Access
TAP-2.5D: A thermally-aware chiplet placement methodology for 2.5D systems
(IEEE, 2021-07-16) Ma, Yenai; Delshadtehrani, Leila; Demirkiran, Cansu; Abellán Miguel, José Luis; Joshi, Ajay; Ingeniería y Tecnología de Computadores; Facultad de Informática
Heterogeneous systems are commonly used today to sustain the historic benefits we have achieved through technology scaling. 2.5D integration technology provides a cost-effective solution for designing heterogeneous systems. The traditional physical design of a 2.5D heterogeneous system closely packs the chiplets to minimize wirelength, but this leads to a thermally-inefficient design. We propose TAP-2.5D: the first open-source network routing and thermally-aware chiplet placement methodology for heterogeneous 2.5D systems. TAP-2.5D strategically inserts spacing between chiplets to jointly minimize the temperature and total wirelength, and in turn, increases the thermal design power envelope of the overall system. We present three case studies demonstrating the usage and efficacy of TAP-2.5D.
Open Access
NeuraChip: accelerating GNN computations with a hash-based decoupled spatial accelerator
(IEEE, 2024-08-01) Shivdikar, Kaustubh; Agostini, Nicolas Bohm; Jayaweera, Malith; Jonatan, Gilbert; Joshi, Ajay; Kim, John; Kaeli, David; Abellán Miguel, José Luis; Facultad de Informática; Ingeniería y Tecnología de Computadores
Graph Neural Networks (GNNs) are emerging as a formidable tool for processing non-euclidean data across various domains, ranging from social network analysis to bioinformatics. Despite their effectiveness, their adoption has not been pervasive because of scalability challenges associated with large-scale graph datasets, particularly when leveraging message passing. They exhibit irregular sparsity patterns, resulting in unbalanced compute resource utilization. Prior accelerators investigating Gustavson’s technique adopted look-ahead buffers for prefetching data, aiming to prevent compute stalls. However, these solutions lead to inefficient use of the on-chip memory, leading to redundant data residing in cache. To tackle these challenges, we introduce NeuraChip, a novel GNN spatial accelerator based on Gustavson’s algorithm. NeuraChip decouples the multiplication and addition computations in sparse matrix multiplication. This separation allows for independent exploitation of their unique data dependencies, facilitating efficient resource allocation. We introduce a rolling eviction strategy to mitigate data idling in on-chip memory as well as address the prevalent issue of memory bloat in sparse graph computations. Furthermore, the compute resource load balancing is achieved through a dynamic reseeding hash-based mapping, ensuring uniform utilization of computing resources agnostic of sparsity patterns. Finally, we present NeuraSim, an open-source, cycle-accurate, multi-threaded, modular simulator for comprehensive performance analysis. Overall, NeuraChip presents a significant improvement, yielding an average speedup of 22.1× over Intel’s MKL, 17.1× over NVIDIA’s cuSPARSE, 16.7× over AMD’s hipSPARSE, and 1.5× over prior state of-the-art SpGEMM accelerator and 1.3× over GNN accelerator. The source code for our open-sourced simulator and performance visualizer is publicly accessible on GitHub.
Open Access
Flexagon: a multi-dataflow sparse-sparse matrix multiplication accelerator for efficient DNN processing
(Association for Computing Machinery, 2023-03-25) Garg, Raveesh; Pellauer, Michael; Krishna, Tushar; Muñoz Martínez, Francisco; Abellán Miguel, José Luis; Acacio Sánchez, Manuel Eugenio; Ingeniería y Tecnología de Computadores; Facultad de Informática
Sparsity is a growing trend in modern DNN models.Existing Sparse-Sparse Matrix Multiplication (SpMSpM) accel-erators are tailored to a particular SpMSpM dataflow (i.e., InnerProduct, Outer Product or Gustavson’s), which determines theiroverall efficiency. We demonstrate that this static decision inher-ently results in a suboptimal dynamic solution. This is becausedifferent SpMSpM kernels show varying features (i.e., dimensions,sparsity pattern, sparsity degree), which makes each dataflow bettersuited to different data sets.In this work we present Flexagon, the first SpMSpM reconfig-urable accelerator that is capable of performing SpMSpM computa-tion by using the particular dataflow that best matches each case.Flexagon accelerator is based on a novel Merger-Reduction Net-work (MRN) that unifies the concept of reducing and merging inthe same substrate, increasing efficiency. Additionally, Flexagonalso includes a new L1 on-chip memory organization, specificallytailored to the different access characteristics of the input and out-put compressed matrices. Using detailed cycle-level simulation ofcontemporary DNN models from a variety of application domains,we show that Flexagon achieves average performance benefits of4.59×, 1.71×, and 1.35×with respect to the state-of-the-art SIGMA-like, SpArch-like and GAMMA-like accelerators (265%, 67%, and18%, respectively, in terms of average performance/area efficiency).
Open Access
Griffin: hardware-software support for efficient page migration in Multi-GPU systems
(IEEE, 2020-04-16) Baruah, Trinayan; Sun, Yifan; Dinçer, Ali Tolga; Mojumder, Saiful A.; Abellán Miguel, José Luis; Ukidave, Yash; Joshi, Ajay; Rubin, Norman; Kim, John; Kaeli, David; Ingeniería y Tecnología de Computadores; Facultad de Informática
As transistor scaling becomes increasingly more difficult to achieve, scaling the core count on a single GPU chip has also become extremely challenging. As the volume of data to process in today's increasingly parallel workloads continues to grow unbounded, we need to find scalable solutions that can keep up with this increasing demand. To meet the need of modern-day parallel applications, multi-GPU systems offer a promising path to deliver high performance and large memory capacity. However, multi-GPU systems suffer from performance issues associated with GPU-to-GPU communication and data sharing, which severely impact the benefits of multi-GPU systems. Programming multi-GPU systems has been made considerably simpler with the advent of Unified Memory which enables runtime migration of pages to the GPU on demand. Current multi-GPU systems rely on a first-touch Demand Paging scheme, where memory pages are migrated from the CPU to the GPU on the first GPU access to a page. The data sharing nature of GPU applications makes deploying an efficient programmer-transparent mechanism for inter-GPU page migration challenging. Therefore following the initial CPU-to-GPU page migration, the page is pinned on that GPU. Future accesses to this page from other GPUs happen at a cache-line granularity - pages are not transferred between GPUs without significant programmer intervention. We observe that this mechanism suffers from two major drawbacks: 1) imbalance in the page distribution across multiple GPUs, and 2) inability to move the page to the GPU that uses it most frequently. Both of these problems lead to load imbalance across GPUs, degrading the performance of the multi-GPU system. To address these problems, we propose Griffin, a holistic hardware-software solution to improve the performance of NUMA multi-GPU systems. Griffin introduces programmer-transparent modifications to both the IOMMU and GPU architecture, supporting efficient runtime page migration based on locality information. In particular, Griffin employs a novel mechanism to detect and move pages at runtime between GPUs, increasing the frequency of resolving accesses locally, which in turn improves the performance. To ensure better load balancing across GPUs, Griffin employs a Delayed First-Touch Migration policy that ensures pages are evenly distributed across multiple GPUs. Our results on a diverse set of multi-GPU workloads show that Griffin can achieve up to a 2.9× speedup on a multi-GPU system, while incurring low implementation overhe
Open Access
Spartan: a sparsity-adaptive framework to accelerate deep neural network training on GPUs
(Institute of Electrical and Electronics Engineers, 2021-03-22) Dong, Shi; Sun, Yifan; Agostini, Nicolas Bohm; Karimi, Elmira; Lowell, Daniel; Zhou, Jing; Cano, José; Abellán Miguel, José Luis; Kaeli, David; Ingeniería y Tecnología de Computadores; Facultad de Informática
Deep Neural Networks (DNNs) have emerged as an important class of machine learning algorithms, providing accurate solutions to a broad range of applications. Sparsity in activation maps in DNN training presents an opportunity to reduce computations. However, exploiting activation sparsity presents two major challenges: i) profiling activation sparsity during training comes with significant overhead due to computing the degree of sparsity and the data movement; ii) the dynamic nature of activation maps requires dynamic dense-to-sparse conversion during training, leading to significant overhead. In this article, we present Spartan, a lightweight hardware/software framework to accelerate DNN training on a GPU. Spartan provides a cost-effective and programmer-transparent microarchitectural solution to exploit activation sparsity detected during training. Spartan provides an efficient sparsity monitor, a tile-based sparse GEMM algorithm, and a novel compaction engine designed for GPU workloads. Spartan can reduce sparsity profiling overhead by 52.5× on average. For the most compute-intensive layers, i.e., convolutional layers, we can speedup AlexNet by 3.4×, VGGNet-16 by 2.14×, and ResNet-18 by 2.02×, when training on the ImageNet dataset.