Browsing by Subject "Synchronization"

Now showing 1 - 3 of 3
  • Thumbnail Image
    Publication
    Open Access
    Regional business cycle phases in Spain
    (2019-06-04) Camacho, Maximo; Pacce, Matias; Ulloa, Camilo; Métodos Cuantitativos para la Economía y la Empresa
    We characterize regional business cycles for Spain using monthly Social Security affiliations. Based on a set of Markov-switching models, we find substantial synchronization of regional business cycles, which has increased since the Great Recession. We do however evidence a regional leading and lagging performance that repeats itself across the different recessions. Typically, earlier signals of national recessions appear in the Islands and Valencia, and are propagated from the periphery to the center. Moreover, north-western regions tend to start the regional recoveries with a significant lag.
  • Thumbnail Image
    Publication
    Open Access
    Splash-4: A Modern Benchmark Suite with Lock-Free Constructs
    (IEEE Computer Society, 2022) Gómez-Hernández, Eduardo José; Cebrian, Juan Manuel; Kaxiras, Stefanos; Ros, Alberto; Ingeniería y Tecnología de Computadores
    The cornerstone for the performance evaluation of computer systems is the benchmark suite. Among the many benchmark suites used in high-performance computing and multicore research, Splash-2 has been instrumental in advancing knowledge for both academia and industry. Published in 1995 and with over 5276 citations and counting, this benchmark suite is still in use to evaluate novel architectural proposals. Recently, the Splash-3 suite eliminates important performance bugs, data races, and improper synchronization that plagued Splash-2 benchmarks after the formal definition of the C memory model. However, keeping up with architectural changes while maintaining the same workloads and algorithms (for comparative purposes) is a real challenge. Benchmark suites can misrepresent the performance characteristics of a computer system if they do not reflect the available features of the hardware and architects may end up overestimating the impact of proposed techniques or underestimating others. In this work we introduce a revised version of Splash-3, designated Splash-4, that introduces modern programming techniques to improve scalability on contemporary hardware. We then characterize Splash-3 and Splash-4 in a state-of-the-art simulated architecture, Intel’s Ice Lake with gem5-20 simulator, as well as a real contemporary hardware processor (AMD’s EPYC 7002 series). Our evaluation shows that for a 64-thread execution Splash-4 reduces the normalized execution time by an average of 52% and 34% for AMD’s EPYC and Intel’s Ice Lake, respectively.
  • Thumbnail Image
    Publication
    Open Access
    Splash-4: Improving Scalability with Lock-Free Constructs
    (2021-04) Gómez-Hernández, Eduardo José; Shao, Ruixiang; Sakalis, Christos; Kaxiras, Stefanos; Ros, Alberto; Ingeniería y Tecnología de Computadores
    Over the past three decades, the parallel applications of the Splash-2 benchmark suite have been instrumental in advancing multiprocessor research. Recently, the Splash-3 benchmarks eliminated performance bugs, data races, and improper synchronization that plagued Splash-2 benchmarks after the definition of the C memory model. In this work, we revisit the Splash-3 benchmarks and adapt them for contemporary architectures with atomic operations and lock-free constructs. With our changes, we improve the scalability of most benchmarks for up to 32 and 64 cores, showing an improvement of up to 9x in actual machines, and up to 5x in simulation, over the unmodified Splash-3 benchmarks. To denote the substantive nature of the improvements in the Splash-3 benchmarks and to re-introduce them in contemporary research, we refer to the new collection as Splash-4.