Publication:
Static Instruction Scheduling for High Performance on Limited Hardware

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dc.contributor.authorTran, Kim-Anh
dc.contributor.authorCarlson, Trevor E.
dc.contributor.authorKoukos, Konstantinos
dc.contributor.authorSjälander, Magnus
dc.contributor.authorSpiliopoulos, Vasileios
dc.contributor.authorKaxiras, Stefanos
dc.contributor.authorJimborean, Alexandra
dc.contributor.departmentIngeniería y Tecnología de Computadores
dc.date.accessioned2024-02-06T13:16:34Z
dc.date.available2024-02-06T13:16:34Z
dc.date.issued2018-04-01
dc.description© 2018. IEEE. This document is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0 This document is the accepted version of a published work that appeared in final form in IEEE Transactions on Computers, vol. 67, no. 4, pp. 513-527 To access the final work, see DOI:, https://doi.org/10.1109/TC.2017.2769641
dc.description.abstractComplex out-of-order (OoO) processors have been designed to overcome the restrictions of outstanding long-latency misses at the cost of increased energy consumption. Simple, limited OoO processors are a compromise in terms of energy consumption and performance, as they have fewer hardware resources to tolerate the penalties of long-latency loads. In worst case, these loads may stall the processor entirely. We present Clairvoyance, a compiler based technique that generates code able to hide memory latency and better utilize simple OoO processors. By clustering loads found across basic block boundaries, Clairvoyance overlaps the outstanding latencies to increases memory-level parallelism. We show that these simple OoO processors, equipped with the appropriate compiler support, can effectively hide long-latency loads and achieve performance improvements for memory-bound applications. To this end, Clairvoyance tackles (i) statically unknown dependencies, (ii) insufficient independent instructions, and (iii) register pressure. Clairvoyance achieves a geomean execution time improvement of 14 percent for memory-bound applications, on top of standard O3 optimizations, while maintaining compute-bound applications' high-performance.es
dc.formatapplication/pdfes
dc.format.extent15es
dc.identifier.citationIEEE Transactions on Computers, vol. 67, no. 4, pp. 513-527
dc.identifier.doihttps://doi.org/10.1109/TC.2017.2769641
dc.identifier.issnPrint: 0018-9340
dc.identifier.issnElectronic: 1557-9956
dc.identifier.urihttp://hdl.handle.net/10201/138783
dc.languageenges
dc.publisherIEEEes
dc.relationThis work is supported, in part, by the Swedish ResearchCouncil UPMARC Linnaeus Centre and by the Swedish VR(grant no. 2016-05086)es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8094900
dc.rightsinfo:eu-repo/semantics/openAccesses
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectCompilerses
dc.subjectCode generationes
dc.subjectMemory managementes
dc.subjectOptimizationes
dc.titleStatic Instruction Scheduling for High Performance on Limited Hardwarees
dc.typeinfo:eu-repo/semantics/articlees
dspace.entity.typePublicationes
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