DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory

Titos-Gil, Rubén; Fernández-Pascual, Ricardo; Acacio Sánchez, Manuel Eugenio; Ros, Alberto

Publication:
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory

dc.contributor.author	Titos-Gil, Rubén
dc.contributor.author	Fernández-Pascual, Ricardo
dc.contributor.author	Acacio Sánchez, Manuel Eugenio
dc.contributor.author	Ros, Alberto
dc.contributor.department	Ingeniería y Tecnología de Computadores
dc.date.accessioned	2021-12-02T20:26:00Z
dc.date.available	2021-12-02T20:26:00Z
dc.date.issued	2022-01
dc.description.abstract	Commercial Hardware Transactional Memory (HTM) systems are best-effort designs that leverage the coherence substrate to detect conflicts eagerly. Resolving conflicts in favor of the requesting core is the simplest option for ensuring deadlock freedom, yet it is prone to livelocks. In this work, we propose and evaluate DeTraS (Delayed Transactional Stores), an HTM-aware store buffer design aimed at mitigating such livelocks. DeTraS takes advantage of the fact that modern commercial processors implement a large store buffer, and uses it to prevent transactional stores predicted to conflict from performing early in the transaction. By leveraging existing processor structures, we propose a simple design that improves the ability of requester-wins HTM systems to achieve forward progress in spite of high contention while side-stepping the performance penalty of falling back to mutual exclusion. With just over 50 extra bytes, DeTraS captures the advantages of lazy conflict management without the complexity brought into the coherence fabric by commit arbitration schemes nor the relaxation of the single-writer invariant of prior works. Through detailed simulations of a 16-core tiled CMP using gem5, we demonstrate that DeTraS brings reductions in average execution time of 25% when compared to an Intel RTM-like design.	es
dc.format	application/pdf	es
dc.format.extent	13	es
dc.identifier.citation	IEEE Transactions on Parallel and Distributed Systems (TPDS), 33 (1)
dc.identifier.doi	10.1109/TPDS.2021.3085210
dc.identifier.issn	1045-9219
dc.identifier.uri	http://hdl.handle.net/10201/114665
dc.language	eng	es
dc.relation	European Research Council (ERC) under the European Union s Horizon 2020 research and innovation programme (ECHO: Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures, grant agreement No 819134, Consolidator Grant, 2018).	es
dc.rights	info:eu-repo/semantics/openAccess	es
dc.rights	Atribución 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by/4.0/	*
dc.subject	Hardware Transactional Memory	es
dc.subject	Store buffer	es
dc.subject	Delay	es
dc.title	DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory	es
dc.type	info:eu-repo/semantics/article	es
dspace.entity.type	Publication	es