Wrong-Path-Aware Entangling Instruction Prefetcher

Ros, Alberto

Publication:
Wrong-Path-Aware Entangling Instruction Prefetcher

dc.contributor	Jimborean, Alexandra
dc.contributor.author	Ros, Alberto
dc.contributor.department	Ingeniería y Tecnología de Computadores
dc.date.accessioned	2023-12-11T12:19:10Z
dc.date.available	2023-12-11T12:19:10Z
dc.date.issued	2024
dc.description	© 2023.IEEE. This document is made available under the CC-BY 4.0 license http://creativecommons.org/licenses/by /4.0/ This document is the Accepted version of a Published Work that appeared in final form in IEEE Transactions on Computers. To access the final edited and published work see DOI 10.1109/TC.2023.3337308	es
dc.description.abstract	Instruction prefetching is instrumental for guaranteeing a high flow of instructions through the processor front end for applications whose working set does not fit in the lowerlevel caches. Examples of such applications are server workloads, whose instruction footprints are constantly growing. There are two main techniques to mitigate this problem: fetch directed prefetching (or decoupled front end) and instruction cache (L1I) prefetching. This work extends the state-of-the-art Entangling prefetcher to avoid training during wrong-path execution. Our Entangling wrong-path-aware prefetcher is equipped with microarchitectural techniques that eliminate more than 99% of wrong-path pollution, thus reaching 98.9% of the performance of an ideal wrongpath-aware solution. Next, we propose two microarchitectural optimizations able to further increase performance benefits by 1.8%, on average. All this is achieved with just 304 bytes. Finally, we study the interplay between the L1I prefetcher and a decoupled front end. Our analysis shows that due to pollution caused by wrong-path instructions, the degree of decoupling cannot be increased unlimitedly without negative effects on the energy-delay product (EDP). Furthermore, the closer to ideal is the L1I prefetcher, the less decoupling is required. For example, our Entangling prefetcher reaches an optimal EDP with a decoupling degree of 64 instructions.	es
dc.format	application/pdf	es
dc.format.extent	12	es
dc.identifier.citation	IEEE Transactions on computers
dc.identifier.doi	10.1109/TC.2023.3337308
dc.identifier.uri	http://hdl.handle.net/10201/136528
dc.language	eng	es
dc.publisher	Institute of Electrical and Electronics Engineers	es
dc.relation	This project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (grant agreement No 819134), MCIN/AEI/10.13039/501100011033/ and the “ERDF A way of making Europe”, EU (grant PID2022- 136315OB-I00), MCIN/AEI/10.13039/501100011033 and the European Union NextGenerationEU/PRTR (grant TED2021- 130233B-C33), and the Ramon y Cajal Research Contract ´ RYC2018-025200-I	es
dc.rights	info:eu-repo/semantics/openAccess	es
dc.rights	Atribución 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by/4.0/	*
dc.subject	Instruction prefetching	es
dc.subject	Processor front-end	es
dc.subject	Performance	es
dc.subject	Energy efficiency	es
dc.title	Wrong-Path-Aware Entangling Instruction Prefetcher	es
dc.type	info:eu-repo/semantics/article	es
dspace.entity.type	Publication	es