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Free Atomics: Hardware Atomic Operations without Fences

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dc.contributor.authorAsgharzadeh, Ashkan
dc.contributor.authorCebrian, Juan M.
dc.contributor.authorPerais, Arthur
dc.contributor.authorKaxiras, Stefanos
dc.contributor.authorRos, Alberto
dc.contributor.departmentIngeniería y Tecnología de Computadores
dc.date.accessioned2022-10-21T10:29:59Z
dc.date.available2022-10-21T10:29:59Z
dc.date.issued2022-06-11
dc.description© 2022. The authors. This document is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0 This document is the accepted version of a published work that appeared in final form in ISCA '22: The 49th Annual International Symposium on Computer Architecture New York New York. To access the final work, see DOI: https://doi.org/10.1145/3470496.3527385
dc.description.abstractAtomic Read-Modify-Write (RMW) instructions are primitive synchronization operations implemented in hardware that provide the building blocks for higher-abstraction synchronization mechanisms to programmers. According to publicly available documentation, current x86 implementations serialize atomic RMW operations, i.e., the store buffer is drained before issuing atomic RMWs and subsequent memory operations are stalled until the atomic RMW commits. This serialization, carried out by memory fences, incurs a performance cost which is expected to increase with deeper pipelines. This work proposes Free atomics, a lightweight, speculative, deadlock-free implementation of atomic operations that removes the need for memory fences, thus improving performance, while preserving atomicity and consistency. Free atomics is, to the best of our knowledge, the first proposal to enable store-to-load forwarding for atomic RMWs. Free atomics only requires simple modifications and incurs a small area overhead (15 bytes). Our evaluation using gem5-20 shows that, for a 32-core configuration, Free atomics improves performance by 12.5%, on average, for a large range of parallel workloads and 25.2%, on average, for atomic-intensive parallel workloads over a fenced atomic RMW implementation.es
dc.formatapplication/pdfes
dc.format.extent13es
dc.identifier.citationISCA '22: The 49th Annual International Symposium on Computer Architecture New York New York Pages 14–26
dc.identifier.doihttps://doi.org/10.1145/3470496.3527385
dc.identifier.eissn978-1-4503-8610-4
dc.identifier.issn1063-6897
dc.identifier.urihttp://hdl.handle.net/10201/124764
dc.languageenges
dc.publisherAssociation for Computing Machinery
dc.relationEuropean Research Council (ERC) under the European Union s Horizon 2020 research and innovation programme (ECHO: Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures, grant agreement No 819134, Consolidator Grant, 2018).es
dc.relation.ispartof49th International Symposium on Computer Architecture (ISCA)es
dc.relation.publisherversionhttps://dl.acm.org/doi/10.1145/3470496.3527385
dc.rightsinfo:eu-repo/semantics/openAccesses
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectMulti-core architectureses
dc.subjectMicroarchitecturees
dc.subjectAtomic Read-Modify-Write instructionses
dc.subjectTotal-Store-Order (TSO)es
dc.subjectStore-to-load forwardinges
dc.titleFree Atomics: Hardware Atomic Operations without Fenceses
dc.typeinfo:eu-repo/semantics/articlees
dspace.entity.typePublicationes
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