A hybrid static-dynamic classification for dual-consistency cache coherence

Jimborean, Alexandra; Ros Bardisa, Alberto

Publication:
A hybrid static-dynamic classification for dual-consistency cache coherence

dc.contributor.author	Jimborean, Alexandra
dc.contributor.author	Ros Bardisa, Alberto
dc.contributor.department	Ingeniería y Tecnología de Computadores
dc.date.accessioned	2024-02-08T12:09:02Z
dc.date.available	2024-02-08T12:09:02Z
dc.date.issued	2016
dc.description	Ros, A., & Jimborean, A. (2016). A hybrid static-dynamic classification for dual-consistency cache coherence. IEEE Transactions on Parallel and Distributed Systems, 27(11), 3101-3115.	es
dc.description.abstract	Traditional cache coherence protocols manage all memory accesses equally and ensure the strongest memory model, namely, sequential consistency. Recent cache coherence protocols based on self-invalidation advocate for the model sequential consistency for data-race-free, which enables powerful optimizations for race-free code. However, for racy code these cache coherence protocols provide sub-optimal performance compared to traditional protocols. This paper proposes SPEL++, a dual-consistency cache coherence protocol that supports two execution modes: a traditional sequential-consistent protocol and a protocol that provides weak consistency (or sequential consistency for data-race-free). SPEL++ exploits a static-dynamic hybrid classification of memory accesses based on (i) a compile-time identification of extended data-race-free code regions for OpenMP applications and (ii) a runtime classification of accesses based on the operating system’s memory page management. By executing racy code under the sequential-consistent protocol and race-free code under the cache coherence protocol that provides sequential consistency for data-race-free, the end result is an efficient execution of the applications while still providing sequential consistency. Compared to a traditional protocol, we show improvements in performance from 19% to 38% and reductions in energy consumption from 47% to 53%, on average for different benchmark suites, on a 64-core chip multiprocessor	es
dc.format	application/pdf	es
dc.format.extent	14	es
dc.identifier.citation	IEEE Transactions on Parallel and Distributed Systems, 27(11), 3101-3115.
dc.identifier.doi	10.1109/TPDS.2016.2528241
dc.identifier.issn	1045-9219
dc.identifier.uri	http://hdl.handle.net/10201/138999
dc.language	eng	es
dc.publisher	IEEE	es
dc.relation	This work was supported in part by the ”Fundaci´on Seneca- Agencia de Ciencia y Tecnolog´ıa de la Regi´on de Murcia” under grant ”J´ovenes L´ıderes en Investigaci´on” 18956/JLI/13, as well as by the Swedish Research Council UPMARC Linnaeus Centre, the VR frame project ”Efficient Modeling of Heterogeneity in the Era of Dark Silicon”: 106201305/C0533201 and by the European 7th Framework Programme (EU ICT-287759) through a collaboration grant from HiPEAC.	es
dc.relation.publisherversion	http://webs.um.es/aros/papers/pdfs/aros-tpds16.pdf	es
dc.rights	info:eu-repo/semantics/openAccess	es
dc.rights	Attribution-NonCommercial-NoDerivatives 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/4.0/	*
dc.subject	Multiprocessors	es
dc.subject	Cache coherence	es
dc.subject	Classification of accesses	es
dc.subject	Runtime	es
dc.subject	Compiler	es
dc.subject	Consistency model	es
dc.subject	Data races	es
dc.title	A hybrid static-dynamic classification for dual-consistency cache coherence	es
dc.type	info:eu-repo/semantics/article	es
dspace.entity.type	Publication	es