Hardware cache locking for all memory updates

Asgharzadeh, Ashkan; Gómez Hernández, Eduardo José; Cebrián, Juan M.; Kaxiras, Stefanos; Ros Bardisa, Alberto

Publication:
Hardware cache locking for all memory updates

dc.contributor.author	Asgharzadeh, Ashkan
dc.contributor.author	Gómez Hernández, Eduardo José
dc.contributor.author	Cebrián, Juan M.
dc.contributor.author	Kaxiras, Stefanos
dc.contributor.author	Ros Bardisa, Alberto
dc.contributor.department	Ingeniería y Tecnología de Computadores
dc.date.accessioned	2024-12-18T07:46:49Z
dc.date.available	2024-12-18T07:46:49Z
dc.date.issued	2024
dc.description	© 2024 IEEE. This document is the Submitted Published version of a Published Work that appeared in final form in 42th IEEE International Conference on Computer Design (ICCD 2024). To access the final edited and published work see https://doi.org/10.1109/ICCD63220.2024.00092	es
dc.description.abstract	Many applications need to perform operations thatinvolve reading a value from memory, modifying it, and thenwriting it back. Multiple architectures provide hardware supportfor these operations via read-modify-write (RMW) instructions.The primary benefit is that the read can request a cacheline withwrite permissions, reducing coherence protocol overhead sincethe write will find the cacheline with appropriate permissions.RMWs can be either atomic or non-atomic. Atomic RMWs, usedfor synchronization, commonly require (i) locking the cacheline toguarantee atomicity by preventing invalidations and (ii) enforcingserialization of instructions in the program (e.g., via memoryfences), which may cause performance degradation based onthe implemented memory consistency model. Non-atomic RMWs,while not requiring such strict measures, should only be used indata-race free code sections. However, other cores may invalidatea cacheline during a non-atomic RMW (e.g., due to false sharing),flushing the pipeline and causing the loss of write permissionsobtained by the read, which is detrimental to performance.In this work, we propose a microarchitectural mechanismthat enables non-atomic RMWs to fetch the cacheline lockingit, thus preventing other cores from “stealing” the cachelinewhile allowing them to run concurrently with other instructionsin the same core. Our proposal enables concurrent hardwarecache locking for multiple non-atomic RMWs while guaranteeingdeadlock freedom and no programmer/compiler intervention.We also propose alock-chainingmechanism to allow multipleconsecutive memory updates to the same cacheline up to apredefined maximum (to prevent starvation and load imbalance).Our evaluation using gem5 full-system simulator shows that foran eight-core configuration, our proposal improves performanceby up to 5.36% (2.05% on average), requiring just 45 bytes ofstorage per core.	es
dc.format	application/pdf	es
dc.format.extent	9	es
dc.identifier.doi	https://doi.org/10.1109/ICCD63220.2024.00092
dc.identifier.eissn	979-8-3503-8040-8
dc.identifier.uri	http://hdl.handle.net/10201/147577
dc.language	eng	es
dc.publisher	IEEE Computer Society	es
dc.relation	This project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation program (grant agreement No 819134), from the MCIN/AEI/10.13039/501100011033/ and the “ERDF A way of making Europe”, EU (grant PID2022-136315OB-I00), and from the MCIN/AEI/10.13039/501100011033/ and the European Union NextGenerationEU/PRTR (grant TED2021-130233BC33).	es
dc.relation.ispartof	42th IEEE International Conference on Computer Design (ICCD 2024), November 18-20, Milan, pp. 566--574	es
dc.rights.accessRights	info:eu-repo/semantics/restrictedAccess
dc.subject	Multi core architectures	es
dc.subject	Micro architecture	es
dc.subject	Non atomic read modify write	es
dc.subject	False sharing	es
dc.subject	Hardware cache locking	es
dc.title	Hardware cache locking for all memory updates	es
dc.type	info:eu-repo/semantics/article	es
dspace.entity.type	Publication	es