Browsing by Subject "multi-copy atomicity"

Now showing 1 - 1 of 1
  • Thumbnail Image
    Publication
    Open Access
    Speculative Enforcement of Store Atomicity
    (2020-10) Ros, Alberto; Kaxiras, Stefanos; Ingeniería y Tecnología de Computadores
    Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see its own stores while they are in limbo, i.e., executed (and perhaps retired) but not yet inserted in memory order. This is known as store-to-load forwarding and it is a necessity to safeguard the local thread’s sequential program semantics while achieving high performance.However, this can lead to counter-intuitive behaviours, requiring fences to prevent such behaviours when needed.Other vendors (e.g., IBM 370 and the z/Architecture series)opt for enforcing what we call in this work store atomicity, that is, disallowing a core to see its own stores before they are written to memory, trading off performance for a more intuitive memory model. Ideally, we want a stricter model to ease programability at the same time that architects can provide high-performance solutions. We make a simple observation. What holds for any other rule in a consistency model, also holds for store atomicity: it is not a crime to break the rule, unless we get caught.In this work, we detail the different ways of detecting a store atomicity violation. This leads us to a new insight: a load performed by a forwarding from an in-limbo store is not speculative; younger loads performed after that forwarding are. Based on this insight we propose an effective and cheap speculative approach to dynamically enforce store atomicity only when the detection of its violation actually occurs. In practice, these cases are rare during the execution of a program. In all other cases (the bulk of the execution of a program) store-to-load forwarding can be done without violating store atomicity.The end result is that we provide the best of both worlds: amore intuitive store-atomic memory model, i.e., the 370 model,with the performance and cost approaching (at an average of just2.5% and 2.7% overhead for parallel and sequential applications,respectively) that of a non-store-atomic model, i.e., the x86 model.