Browsing by Subject "Cache coherence"

Now showing 1 - 3 of 3
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    A hybrid static-dynamic classification for dual-consistency cache coherence
    (IEEE, 2016) Jimborean, Alexandra; Ros Bardisa, Alberto; Ingeniería y Tecnología de Computadores
    Traditional cache coherence protocols manage all memory accesses equally and ensure the strongest memory model, namely, sequential consistency. Recent cache coherence protocols based on self-invalidation advocate for the model sequential consistency for data-race-free, which enables powerful optimizations for race-free code. However, for racy code these cache coherence protocols provide sub-optimal performance compared to traditional protocols. This paper proposes SPEL++, a dual-consistency cache coherence protocol that supports two execution modes: a traditional sequential-consistent protocol and a protocol that provides weak consistency (or sequential consistency for data-race-free). SPEL++ exploits a static-dynamic hybrid classification of memory accesses based on (i) a compile-time identification of extended data-race-free code regions for OpenMP applications and (ii) a runtime classification of accesses based on the operating system’s memory page management. By executing racy code under the sequential-consistent protocol and race-free code under the cache coherence protocol that provides sequential consistency for data-race-free, the end result is an efficient execution of the applications while still providing sequential consistency. Compared to a traditional protocol, we show improvements in performance from 19% to 38% and reductions in energy consumption from 47% to 53%, on average for different benchmark suites, on a 64-core chip multiprocessor
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    Automatic detection of large extended data-race-free regions with conflict isolation
    (Institute of Electrical and Electronics Engineers, 2018-03) Jimborean, Alexandra; Ekemark, Per; Waern, Jonatan; Kaxiras, Stefanos; Ros, Alberto; Ingeniería y Tecnología de Computadores
    Data-race-free (DRF) parallel programming becomes a standard as newly adopted memory models of mainstream programming languages such as C++ or Java impose data-race-freedom as a requirement. We propose compiler techniques that automatically delineate extended data-race-free (xDRF) regions, namely regions of code that provide the same guarantees as the synchronization-free regions (in the context of DRF codes). xDRF regions stretch across synchronization boundaries, function calls and loop back-edges and preserve the data-race-free semantics, thus increasing the optimization opportunities exposed to the compiler and to the underlying architecture. We further enlarge xDRF regions with a conflict isolation (CI) technique, delineating what we call xDRF-CI regions while preserving the same properties as xDRF regions. Our compiler (1) precisely analyzes the threads’ memory accessing behavior and data sharing in shared-memory, general-purpose parallel applications, (2) isolates data-sharing and (3) marks the limits of xDRF-CI code regions. The contribution of this work consists in a simple but effective method to alleviate the drawbacks of the compiler’s conservative nature in order to be competitive with (and even surpass) an expert in delineating xDRF regions manually. We evaluate the potential of our technique by employing xDRF and xDRF-CI region classification in a state-of-the-art, dual-mode cache coherence protocol. We show that xDRF regions reduce the coherence bookkeeping and enable optimizations for performance (6.4%) and energy efficiency (12.2%) compared to a standard directory-based coherence protocol. Enhancing the xDRF analysis with the conflict isolation technique improves performance by 7.1% and energy efficiency by 15.9%.
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    Precise characterization of coherence activity in multicores using gem5
    (Springer, 2025-05-30) Ferrer, Joaquín; Cebrián, Juan M.; Fernández Pascual, Ricardo; Acacio Sánchez, Manuel Eugenio; Ingeniería y Tecnología de Computadores
    Simulation enables cost-effective and rapid prototyping in computer architecture research. It helps assess the impact of architectural changes on performance, area, and energy consumption, playing a crucial role in early-stage development. Gem5 has become a widely used simulation tool in academia and industry for researching multicore architectures. However, its accuracy depends on proper configuration. Key parameters, such as core microarchitecture, memory hierarchy, and interconnection network, must be carefully calibrated to ensure realistic results. This work highlights the importance of a well-adjusted simulation environment for modeling modern multicore setups, with a focus on coherence directory. We refine core, memory, and interconnection parameters, identifying and addressing deficiencies in the simulation infrastructure. We introduce new functionalities and statistics to enhance system characterization. We implement Intel’s Top-Down methodology in gem5, extending it with two new levels to analyze coherence activity’s impact on performance. Lastly, we enable gem5 to support various sparse directory architectures.